- Sprache
-
Englisch
- Anmerkungen
-
Halle (Saale), Univ., Diss., 1999
- Identifier
-
960520406
- Thema
-
Logiksynthese ; Verifikation ; Boolesche Funktion ; NP-vollständiges Problem ; OBDD ; Hochschulschrift; Online-Publikation
- Beteiligte Personen und Organisationen
- URN
- Rechteinformation
-
Der Zugriff auf das Objekt ist unbeschränkt möglich.
- Letzte Aktualisierung
-
26.01.2023, 13:53 MEZ
Datenpartner
Dieses Objekt wird bereitgestellt von:
Deutsche Nationalbibliothek. Bei Fragen zum Objekt wenden Sie sich bitte an den Datenpartner.
Deutsche Nationalbibliothek. Bei Fragen zum Objekt wenden Sie sich bitte an den Datenpartner.
Objekttyp
- Monografie
Beteiligte
Ähnliche Objekte (12)
Automatic signature verification using segmentation
A Modal Logic for Handling Behavioural Constraints in Formal Hardware Verification
Computer logic, testing and verification
Constrained Proofs : A Logic for Dealing with Behavioural Constraints in Formal Hardware Verification
Software verification for programmable logic controllers
Specification and verification of declarative open interaction models : a logic-based approach
An Approach for Hybrid Modelling and Formal Verification in FOCUS
A common approach to test generation and hardware verification based on temporal logic
Efficient signature verification and key revocation using identity based cryptography
Formal verification for ALICA plans
Formal verification of pipelined microprocessors
Formal verification of recursive predicates
Automatic signature verification using segmentation
A Modal Logic for Handling Behavioural Constraints in Formal Hardware Verification
Computer logic, testing and verification
Constrained Proofs : A Logic for Dealing with Behavioural Constraints in Formal Hardware Verification
Software verification for programmable logic controllers
Specification and verification of declarative open interaction models : a logic-based approach
An Approach for Hybrid Modelling and Formal Verification in FOCUS
A common approach to test generation and hardware verification based on temporal logic
Efficient signature verification and key revocation using identity based cryptography
Formal verification for ALICA plans
Formal verification of pipelined microprocessors
Formal verification of recursive predicates
Automatic signature verification using segmentation
A Modal Logic for Handling Behavioural Constraints in Formal Hardware Verification
Computer logic, testing and verification
Constrained Proofs : A Logic for Dealing with Behavioural Constraints in Formal Hardware Verification
Software verification for programmable logic controllers
Specification and verification of declarative open interaction models : a logic-based approach
An Approach for Hybrid Modelling and Formal Verification in FOCUS
A common approach to test generation and hardware verification based on temporal logic
Efficient signature verification and key revocation using identity based cryptography
Formal verification for ALICA plans
Formal verification of pipelined microprocessors