- Sprache
-
Englisch
- Identifier
-
1242413464
- Thema
-
Hardware; Computerarchitektur; Mehrkernprozessor; Hardwareentwurf; Parallelverarbeitung; Worst-Case-Laufzeit
- Beteiligte Personen und Organisationen
-
Frieb, Martin
Ungerer, Theo
- URN
- Rechteinformation
-
Der Zugriff auf das Objekt ist unbeschränkt möglich.
- Letzte Aktualisierung
-
26.01.2023, 13:54 MEZ
Datenpartner
Dieses Objekt wird bereitgestellt von:
Deutsche Nationalbibliothek. Bei Fragen zum Objekt wenden Sie sich bitte an den Datenpartner.
Deutsche Nationalbibliothek. Bei Fragen zum Objekt wenden Sie sich bitte an den Datenpartner.
Objekttyp
- Monografie
Beteiligte
- Frieb, Martin
- Ungerer, Theo
Ähnliche Objekte (12)
Requirements for and design of a processor with predictable timing
Timing analysis for the Precision Timed ARM processor.
Timing-predictable memory allocation in hard real-time systems
parMERASA Pattern Catalogue: Timing Predictable Parallel Design Patterns
IBM PowerNP Network Processor : hardware, software and applications
Efficient and predictable thread synchronization mechanisms for mixed-criticality systems on shared-memory multi-processor platforms
Predictable and Unsatisfying
Timing model derivation : static analysis of hardware description languages
KEP2 (Kiel Esterel Processor 2) THE ESTEREL PROCESSOR
Timing model derivation : pipeline analyzer generation from hardware description languages
Timing model derivation : pipeline analyzer generation from hardware description languages
Billionaires are so Predictable
Requirements for and design of a processor with predictable timing
Timing analysis for the Precision Timed ARM processor.
Timing-predictable memory allocation in hard real-time systems
parMERASA Pattern Catalogue: Timing Predictable Parallel Design Patterns
IBM PowerNP Network Processor : hardware, software and applications
Efficient and predictable thread synchronization mechanisms for mixed-criticality systems on shared-memory multi-processor platforms
Predictable and Unsatisfying
Timing model derivation : static analysis of hardware description languages
KEP2 (Kiel Esterel Processor 2) THE ESTEREL PROCESSOR
Timing model derivation : pipeline analyzer generation from hardware description languages
Timing model derivation : pipeline analyzer generation from hardware description languages
Billionaires are so Predictable
Requirements for and design of a processor with predictable timing
Timing analysis for the Precision Timed ARM processor.
Timing-predictable memory allocation in hard real-time systems
parMERASA Pattern Catalogue: Timing Predictable Parallel Design Patterns
IBM PowerNP Network Processor : hardware, software and applications
Efficient and predictable thread synchronization mechanisms for mixed-criticality systems on shared-memory multi-processor platforms
Predictable and Unsatisfying
Timing model derivation : static analysis of hardware description languages
KEP2 (Kiel Esterel Processor 2) THE ESTEREL PROCESSOR
Timing model derivation : pipeline analyzer generation from hardware description languages
Timing model derivation : pipeline analyzer generation from hardware description languages